Hewlett-Packard years

I did well in college but I had no real idea of what type of engineering I wanted to do. Thanks to the effort of an anonymous professor (I think it was my IC Lab prof) I scored an interview at the Hewlett-Packard facility in Fort Collins in the Technical Workstation Group. I also had no idea I got to interview with one of the best groups under the leadership of Ken Watts. His group was building an 8-bit graphics frame buffer and companion 3D wireframe graphics processor for a high-end workstation. This was at the time where a frame buffer came in it's own enclosure with fans and power supply. The accelerator would bolt on to the enclosure in another box and the whole thing cost something like $20k. I had very little experience with computer graphics (other than playing with a Tektronix storage tube based graphics terminal). At one point in the interview I saw their breadboard prototype running. They had a wireframe tractor driving across a wireframe terrain and I was hooked. I desperately wanted to work on a project like that. Ken gave me an offer at the end of the day and I was in heaven. I started in the spring of 1985.

I was lucky enough to see the tail end of the famed HP-way. The engineers in Fort Collins were top notch and my learning curve was incredibly steep. My first project was as a tester on HP's graphics library called Starbase. Boring and tedious but I learned a lot about computer graphics. Then Ken's group was to start work on a 2D graphics board for the 300 series of unix workstations. I was assigned to work under a crusty but brilliant engineer named Richard Herrington on the rendering chip. He would design the rendering algorithms (lines, polygons and even circles and ellipses) as BASIC programs on an earlier generation HP workstation and then I would decompose them into logical functions and test them in a C-simulation of the graphics board I wrote. The C-simulation actually rendered into a simulated RAM array that I would display on a monitor to verify the board worked as expected. Then I worked with an ASIC designer at HP's Loveland facility named Phil Yastrow to translate my C into gates. There was no other simulation so I evolved my C-simulation to be written in such a way that each C line translated directly into one or more gates. That way we had a pretty good idea that the ASIC functionality met the real specification (the C simulation). The design used a controller that drove datapath ASICs which in turn connected to VRAMs. The analog guy in our group, Desi Rhodan, designed a full-custom RAMDAC (I think just as Brooktree was starting to design their RAMDACs). We used CMOS logic for the ASICs. At that time in HP's history it wasn't uncommon for a HP facility to have its own IC fab. Fort Collins was home to HP's famed NMOS fab and Loveland had a CMOS fab used primarily for analog and instrumentation chips. The NMOS guys were incredibly arrogant and predicted our ASICs would never work unless we used them but we had great success (and lower power requirements) with the Loveland CMOS process. I had a ball working with Phil and we often worked late into the night all alone except for the security guards in this huge facility.

The chipset worked and HP built several graphics boards with the technology serving 2D needs for years with both 68k and PA-RISC workstations. Ken had another group that build a 2D accelerator companion board that would plug on top of the graphics boards. It used a bit-slice integer ALU and 68020 for control. I wanted to work on that project as well but ended up writing a set of demos that went to Siggraph one year.

Ken left to found SAE with Doug MacGregor and I ended up under another manager for a few months. He and I didn't get along and I cannot even remember what I worked on. Ken called me and although I was excited to leave HP, I'm glad I got to be a part that famed company for a few years.

Catseye Graphics Board (6-plane)