My professional life has alternated between hardware design/architecture, ASIC verification and software development. I have been lucky to work at some interesting companies and with some exceptional people. I have found that I enjoy system architecture and design the most. I enjoy seeing a complete system come together and work. In a full-circle turn, I am now building a complete product company.

Giulio Lighting, Boulder, Colorado, 2010-present
Decorative color wash LED lighting. Owner.

  • Managed production including contract manufacturing. Designed manufacturing process including production support software.

  • Implemented commerce capable website.

  • Designed marketing program including collateral material.

danjuliodesigns LLC, Boulder, Colorado, 2006-present
Engineering design. Owner.
  • Ported firmware to a new video diversity receiver.

  • Designed a LED control board combining a buck regulator, high-current switches, Arduino and Xbee transceiver for an artist’s LED sculpture.

  • Developed low-cost distributed control architecture for traditional and color capable light fixtures.

  • Architected wireless protocol for device control using low-power 2.4 Ghz ISM-band transceivers.

  • Designed multiple color-wash LED controllers, bridge interfaces and associated wired and hand-held remote control devices.

  • Developed distributed client/server control system using Java and C++ on Windows, linux, embedded linux and Mac OS X platforms.

  • Built many micro-controller based internal test tools.

  • Designed and built a prototype remote heart rate monitoring system.

TransEDA, Inc., Boulder, Colorado, 2001, 2002-2006
Provided ASIC design verification tools. (Acquired iMODL)
  • Developed System Verilog and PSL assertions as part of a test process for a new analysis tool.

  • Developed PCI Express ASIC verification product. Implemented Verilog, C and C++ components of a verification model and protocol checker with associated documentation, test benches and test programs.

  • Managed outsourced PCI Express protocol compliance monitor project including project definition, architecture, review, validation and final documentation/productization.

  • Ported two large C/C++ projects to operate under 64-bit Solaris and RHEL 3.0 using GCC compilers and tools.

  • Provide product support for several verification models.

Mindspeed, Boulder, Colorado, 2002
Developed ASICs for telecom applications.
  • Implemented module level test bench for a Network Processor ASIC using Cadence Test Builder to develop C++ Transaction Verification Modules and System C to develop cycle accurate behavioral models.

  • Developed system level test bench for an IP-over-SONET ASIC using Verisity Specman. Developed stimulus generator and protocol monitor for SPI-3 and POS PHY 2 interfaces.

iMODL, Inc., Boulder, Colorado, 1999-2001
Provided ASIC design verification tools. (Acquired Bolder Design Labs)
  • Provided input into development of a Java pseudo-random automated test generator. Developed concept of model driver to interface test generator to HDL-based verification models, protocol monitors and test benches.

  • Team lead for continued development, testing and release of PCI verification environment. Architected and began development of PCI/PCI-X verification models and protocol monitor. Created model driver to interface Java pseudo-random test generator to PCI /PCI-X models and protocol monitors.

  • Provided integration support for customers.

Bolder Design Labs, Inc., Boulder, Colorado, 1995-1999
Provided ASIC, system design and verification services. Founder. Secretary of the board.
  • Provided management, budgeting and system administration functions for the company.

  • Architected and implemented a Verilog-based highly configurable pseudo-random test case generator for a Pentium Pro simulation model

  • Architected and developed a PCI verification environment (Verilog with C PLI). Components include test bench, master/slave bus functional model, protocol monitor, vector capture/verification module, pseudo-random simulation test case generator and a detailed set of directed regression tests.

  • Developed psuedo-random verification environment for an 8-way multiprocessor ASIC set.

  • Investigated dynamically re-programmable FPGA technology and integrated microprocessor logic as a vehicle to provide “software” based IO interfaces.

  • Developed directed regression environment and tests for a ring-based multi-node PCI bridge ASIC.

Independent Consultant, 1994-1995
Provided system level simulation services for Unisys Corporation’s Unix Systems Development Group.
  • Wrote and debugged Verilog and Intel simulation test cases for a Pentium based multiprocessor CPU on a proprietary GTL split-transaction bus.

  • Developed Verilog random test case generator as part of a simulation environment for a PCI interface ASIC. All ASICs were fully functional with first pass silicon.

  • Supported 3rd party Pentium Pro simulation model.

  • Designed hardware and firmware for an Orthopedic Limb Load Monitor.

  • Developed firmware test suites and verified firmware operation in accordance with FDA requirements for a class 2 medical device.

Solbourne Computer, Inc., Longmont, Colorado, 1987-1994
Design and manufacture of Sun compatible SPARC-based UNIX workstations and servers.
  • Project Leader for all aspects of the development and introduction of a new line of commercial SMP UNIX servers.

  • Primary architect for the system, including RAS features for the commercial market.

  • Architect and lead engineer for a new SBus based I/O subsystem.

  • Hardware Department Manager for 10-12 people including board level designers, ASIC designers and technicians.

  • Hands on project management of several programs (second generation desktop workstation, quick turn of CPU board, new VME I/O board, technology board).

  • Graphics Hardware Group Manager for five hardware engineers (board and ASIC) and provided project leadership for graphics subsystem development.

  • Managed fast-track development of a low-end accelerated color frame buffer. From start of project to functional prototype took only 2.5 weeks. Board was in production in less than 3 months.

  • Project lead and primary architect for a family of 2-D and 3-D graphics cards with responsibility for hardware, microcode, device drivers and diagnostics.

  • Lead engineer and architect for one of three ASIC designs. Responsible for algorithm design and simulation.

  • Team lead for a group of engineers designing Sun compatible monochrome and color graphics cards for Solbourne multiprocessor systems.

  • Designed a computer controlled stimulus/monitor board capable of executing all transaction types on a proprietary cache-coherent multiprocessor bus.

Hewlett-Packard Corp., Fort Collins, Colorado, 1985-1987
Design and manufacture of technical UNIX workstations.
  • Member of a hardware design team responsible for the development of a family of 2-D graphics subsystems used in HP workstations.

  • Implemented a graphics rendering ASIC. Responsible for algorithm development and verification, gate-level design of portions of the ASIC, C-code RTL level functional simulator, functional and production test vectors and hardware debug.

  • Wrote C-code test routines for verification of the HP Starbase graphics library.

  • Wrote a suite of demonstration programs used to show the performance and features of the graphics subsystem at Siggraph 87.


B.S., Electrical Engineering and Computer Science, University of Colorado, Boulder Colorado, 1984